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this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 1 en29lv160 rev. a, issue date: 2004 / 03 / 30 0. features ? 3.0v, single power supply operation - minimizes system level power requirements ? high performance - access times as fast as 70 ns ? low power consumption (typical values at 5 mhz) - 9 ma typical active read current - 20 ma typical program/erase current - 1 a typical standby current (standard access time to active mode) ? flexible sector architecture: - one 16 kbyte, two 8 kbyte, one 32 kbyte, and thirty-one 64 kbyte sectors (byte mode) - one 8 kword, two 4 kword, one 16 kword and thirty-one 32 kword sectors (word mode) - supports full chip erase - individual sector erase supported - sector protection: hardware locking of sectors to prevent program or erase operations within individual sectors additionally, temporary sector group unprotect allows code changes in previously locked sectors. ? high performance program/erase speed - byte program time: 8s typical - sector erase time: 500ms typical - chip erase time: 17.5s typical ? jedec standard program and erase commands ? jedec standard data polling and toggle bits feature ? single sector and chip erase ? sector unprotect mode ? embedded erase and program algorithms ? erase suspend / resume modes: read and program another sector during erase suspend mode ? 0.23 m triple-metal double-poly triple-well cmos flash technology ? low vcc write inhibit < 2.5v ? >100k program/erase endurance cycle ? package options - 48-pin tsop (type 1) - 48 ball 6mm x 8mm fbga ? commercial temperature range general description the en29lv160 is a 16-megabit, electrically erasable, read/write non-volatile flash memory, organized as 2,097,152 bytes or 1,048,576 words. any byte can be programmed typically in 8s. the en29lv160 features 3.0v voltage read and write operation, with access times as fast as 70ns to eliminate the need for wait states in high-performance microprocessor systems. the en29lv160 has separate output enable ( oe ), chip enable ( ce ), and write enable (we) controls, which eliminate bus contention issues. this device is designed to allow either single sector or full chip erase operation, where each sector can be individually protected against program/erase operations or tempor arily unprotected to erase or pr ogram. the device can sustain a minimum of 100k program/erase cycles on each sector. en29lv160 ******preliminary draft****** 16 megabit (2048k x 8-bit / 1024k x 16 -bit) flash memory boot sector flash memory, cmos 3.0 volt-only
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 2 en29lv160 rev. a, issue date: 2004 / 03 / 30 connection diagrams a6 a5 a4 a1 a3 a2 fbga top view, balls facing down a13 a9 a3 ry/by# we# a7 b6 b5 b4 b1 b3 b2 a12 a8 a4 n c reset# a17 c6 c5 c4 c1 c3 c2 a14 a10 a2 a18 n c a6 d6 d5 d4 d1 d3 d2 a15 a11 a1 n c a19 a5 e6 e5 e4 e1 e3 e2 a16 dq7 a0 dq2 dq5 dq0 f6 f5 f4 f3 f2 byte# dq14 ce# dq10 dq12 dq8 g6 g5 g4 g3 g2 dq15/a-1 dq13 oe# dq11 vcc dq9 h6 h5 h3 h2 vss dq6 vss dq4 dq1 f1 g1 h4 h1 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 standard tsop a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we# reset# nc nc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a 16 byte# vss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# vss ce# a 0
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 3 en29lv160 rev. a, issue date: 2004 / 03 / 30 table 1. pin description figure 1. logic diagram pin name function a0-a19 20 addresses dq0-dq14 15 data inputs/outputs dq15 / a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# chip enable oe# output enable reset# hardware reset pin ry/by# ready/busy output we# write enable vcc supply voltage (2.7-3.6v) vss ground nc not connected to anything byte# byte/word mode en29lv160 dq0 ? dq15 (a-1) a0 ? a19 we ce oe ry/by reset byte
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 4 en29lv160 rev. a, issue date: 2004 / 03 / 30 table 2. sector address tables (en29lv160t) address range (in hexadecimal) sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) byte mode (x8) word mode (x16) sa0 0 0 0 0 0 x x x 62/32 000000?00ffff 00000?07fff sa1 0 0 0 0 1 x x x 64/32 010000?01ffff 08000?0ffff sa2 0 0 0 1 0 x x x 64/32 020000?02ffff 10000?17fff sa3 0 0 0 1 1 x x x 64/32 030000?03ffff 18000?1ffff sa4 0 0 1 0 0 x x x 64/32 040000?04ffff 20000?27fff sa5 0 0 1 0 1 x x x 64/32 050000?05ffff 28000?2ffff sa6 0 0 1 1 0 x x x 64/32 060000?06ffff 30000?37fff sa7 0 0 1 1 1 x x x 64/32 070000?07ffff 38000?3ffff sa8 0 1 0 0 0 x x x 64/32 080000?08ffff 40000?47fff sa9 0 1 0 0 1 x x x 64/32 090000?09ffff 48000?4ffff sa10 0 1 0 1 0 x x x 64/32 0a0000?0affff 50000?57fff sa11 0 1 0 1 1 x x x 64/32 0b0000?0bffff 58000?5ffff sa12 0 1 1 0 0 x x x 64/32 0c0000?0cffff 60000?67fff sa13 0 1 1 0 1 x x x 64/32 0d0000?0dffff 68000?6ffff sa14 0 1 1 1 0 x x x 64/32 0e0000?0effff 70000?77fff sa15 0 1 1 1 1 x x x 64/32 0f0000?0fffff 78000?7ffff sa16 1 0 0 0 0 x x x 64/32 100000?10ffff 80000?87fff sa17 1 0 0 0 1 x x x 64/32 110000?11ffff 88000?8ffff sa18 1 0 0 1 0 x x x 64/32 120000?12ffff 90000?97fff sa19 1 0 0 1 1 x x x 64/32 130000?13ffff 98000?9ffff sa20 1 0 1 0 0 x x x 64/32 140000?14ffff a0000?a7fff sa21 1 0 1 0 1 x x x 64/32 150000?15ffff a8000?affff sa22 1 0 1 1 0 x x x 64/32 160000?16ffff b0000?b7fff sa23 1 0 1 1 1 x x x 64/32 170000?17ffff b8000?bffff sa24 1 1 0 0 0 x x x 64/32 180000?18ffff c0000?c7fff sa25 1 1 0 0 1 x x x 64/32 190000?19ffff c8000?cffff sa26 1 1 0 1 0 x x x 64/32 1a0000?1affff d0000?d7fff sa27 1 1 0 1 1 x x x 64/32 1b0000?1bffff d8000?dffff sa28 1 1 1 0 0 x x x 64/32 1c0000?1cffff e0000?e7fff sa29 1 1 1 0 1 x x x 64/32 1d0000?1dffff e8000?effff sa30 1 1 1 1 0 x x x 64/32 1e0000?1effff f0000?f7fff sa31 1 1 1 1 1 0 x x 32/16 1f0000?1f7fff f8000?fbfff sa32 1 1 1 1 1 1 0 0 8/4 1f8000?1f9fff fc000?fcfff sa33 1 1 1 1 1 1 0 1 8/4 1fa000?1fbfff fd000?fdfff sa34 1 1 1 1 1 1 1 x 16/8 1fc000?1fffff fe000?fffff
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 5 en29lv160 rev. a, issue date: 2004 / 03 / 30 table 3. sector address tables (en29lv160b) address range (in hexadecimal) sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) byte mode (x8) word mode (x16) sa0 0 0 0 0 0 0 0 x 16/8 000000?003fff 00000?01fff sa1 0 0 0 0 0 0 1 0 8/4 004000?005fff 02000?02fff sa2 0 0 0 0 0 0 1 1 8/4 006000?007fff 03000?03fff sa3 0 0 0 0 0 1 x x 32/16 008000?00ffff 04000?07fff sa4 0 0 0 0 1 x x x 64/32 010000?01ffff 08000?0ffff sa5 0 0 0 1 0 x x x 64/32 020000?02ffff 10000?17fff sa6 0 0 0 1 1 x x x 64/32 030000?03ffff 18000?1ffff sa7 0 0 1 0 0 x x x 64/32 040000?04ffff 20000?27fff sa8 0 0 1 0 1 x x x 64/32 050000?05ffff 28000?2ffff sa9 0 0 1 1 0 x x x 64/32 060000?06ffff 30000?37fff sa10 0 0 1 1 1 x x x 64/32 070000?07ffff 38000?3ffff sa11 0 1 0 0 0 x x x 64/32 080000?08ffff 40000?47fff sa12 0 1 0 0 1 x x x 64/32 090000?09ffff 48000?4ffff sa13 0 1 0 1 0 x x x 64/32 0a0000?0affff 50000?57fff sa14 0 1 0 1 1 x x x 64/32 0b0000?0bffff 58000?5ffff sa15 0 1 1 0 0 x x x 64/32 0c0000?0cffff 60000?67fff sa16 0 1 1 0 1 x x x 64/32 0d0000?0dffff 68000?6ffff sa17 0 1 1 1 0 x x x 64/32 0e0000?0effff 70000?77fff sa18 0 1 1 1 1 x x x 64/32 0f0000?0fffff 78000?7ffff sa19 1 0 0 0 0 x x x 64/32 100000?10ffff 80000?87fff sa20 1 0 0 0 1 x x x 64/32 110000?11ffff 88000?8ffff sa21 1 0 0 1 0 x x x 64/32 120000?12ffff 90000?97fff sa22 1 0 0 1 1 x x x 64/32 130000?13ffff 98000?9ffff sa23 1 0 1 0 0 x x x 64/32 140000?14ffff a0000?a7fff sa24 1 0 1 0 1 x x x 64/32 150000?15ffff a8000?affff sa25 1 0 1 1 0 x x x 64/32 160000?16ffff b0000?b7fff sa26 1 0 1 1 1 x x x 64/32 170000?17ffff b8000?bffff sa27 1 1 0 0 0 x x x 64/32 180000?18ffff c0000?c7fff sa28 1 1 0 0 1 x x x 64/32 190000?19ffff c8000?cffff sa29 1 1 0 1 0 x x x 64/32 1a0000?1affff d0000?d7fff sa30 1 1 0 1 1 x x x 64/32 1b0000?1bffff d8000?dffff sa31 1 1 1 0 0 x x x 64/32 1c0000?1cffff e0000?e7fff sa32 1 1 1 0 1 x x x 64/32 1d0000?1dffff e8000?effff sa33 1 1 1 1 0 x x x 64/32 1e0000?1effff f0000?f7fff sa34 1 1 1 1 1 x x x 64/32 1f0000?1fffff f8000?fffff
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 6 en29lv160 rev. a, issue date: 2004 / 03 / 30 product selector guide product number en29lv160 regulated voltage range: vcc=3.0 ? 3.6 v speed option full voltage range: vcc=2.7 ? 3.6 v -70 -90 max access time, ns (t acc ) 70 90 max ce# access, ns (t ce ) 70 90 max oe# access, ns (t oe ) 30 35 block diagram we ce oe state control command register erase voltage generator input/output buffers program voltage generator chip enable output enable logic data latch y-decoder x-decoder y-gating cell matrix timer vcc detector a0-a19 vcc vss dq0-dq15 (a-1) address latch block protect switches stb stb ry/by
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 7 en29lv160 rev. a, issue date: 2004 / 03 / 30 table 3. operating modes 16m flash user mode table dq8-dq15 operation ce# oe# we# reset# a0- a19 dq0-dq7 byte# = v ih byte# = v il read l l h h a in d out d out high-z write l h l h a in d in d in high-z cmos standby v cc 0.3v x x v cc 0.3v x high-z high-z high-z ttl standby h x x h x high-z high-z high-z output disable l h h h x high-z high-z high-z hardware reset x x x l x high-z high-z high-z temporary sector unprotect x x x v id a in d in d in x notes: l=logic low= v il , h=logic high= v ih , v id =11 0.5v, x=don?t care (either l or h, but not floating!), d in =data in, d out =data out, a in =address in table 4. device identifi ction (autoselect codes) 16m flash manufacturer/device id table note: 1. a8=h is recommended for manufacturing id check. if a ma nufacturing id is read with a8=l, the chip will output a configuration code 7fh 2. a9 = vid is for hv a9 autoselect mode only. a9 must be vcc (cmos logic level) for command autoselect mode. description mode a19 to a12 a11 to a10 a9 2 a8 a7 a6 a5 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id: eon l l h x x v id h 1 x l x l l x 1ch word l l h 22h c4h device id (top boot block) byte l l h x x v id xxlxlh x c4h word l l h 22h 49h device id (bottom boot block) byte l l h x x v id xxlxlh x 49h x 01h (protected) sector protection verification l l h sa x v id xxlxh l x 00h (unprotected) oe ce we
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 8 en29lv160 rev. a, issue date: 2004 / 03 / 30 user mode definitions word / byte configuration the signal set on the byte# pin controls whether the device data i/o pins dq15-dq0 operate in the byte or word configuration. when the byte# pin is set at logic ?1?, then the device is in word configuration, dq15-dq0 are active and are controlled by ce# and oe#. on the other hand, if the byte# pin is set at logic ?0?, then the device is in byte configuration, and only data i/o pins dq0-dq7 are active and controlled by ce# and oe#. the data i/o pins dq8- dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. standby mode the en29lv160 has a cmos-compatible standby mode, which reduces the current to < 1a (typical). it is placed in cmos-compatible standby when the ce pin is at v cc 0.5. reset# and byte# pin must also be at cmos input levels. the device also has a ttl-compatible standby mode, which reduces the maximum v cc current to < 1ma. it is placed in ttl-compatible standby when the ce pin is at v ih . when in standby modes, the outputs are in a high-impedance state independent of the oe input. read mode the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more additional information. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. se e the ?reset command? additional details. output disable mode when the ce or oe pin is at a logic high level (v ih ), the output from the en29lv160 is disabled. the output pins are placed in a high impedance state. auto select identification mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq15?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (10.5 v to 11.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are don?t-care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15?dq0.
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 9 en29lv160 rev. a, issue date: 2004 / 03 / 30 to access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see ?command definitions? for details on using the autoselect mode. write mode programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embe dded program al gorithm. the system is not required to provide further controls or timings. the device au tomatically provides internally generated program pulses and verifies the programmed cell margin. the command definitions in table 5 show the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. see ?write operation status? for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may halt the operation and set dq5 to ?1?, or cause the data# polling algorithm to indicate the operation was succ essful. however, a succ eeding read will show that the data is still ?0?. only erase operations ca n convert a ?0? to a ?1?. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables bo th program and erase operations in previously protected sectors. there are two methods to enabling this hardware protection circuitry. the first one requires only that the reset# pin be at v id and then standard microprocessor timings can be used to enable or disable this feature. see flowchart 7a and 7b for the algorithm and figure 12 for the timings. when doing sector unprotect, all the other sectors should be protected first. the second method is meant for programming equipment. this method requires v id be applied to both oe# and a9 pin and non-standard microprocessor timings are used. this method is described in a separate document called en29lv160 supplement, which can be obtained by contacting a representative of e on silicon solution, inc. temporary sector unprotect this feature allows temporary unprotection of previously protected sector groups to change data while in-system. the sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by simply selecting the sector addresses. once is removed from the reset# pin, all the previously protected sectors are protected again. see accompanying figure and timing diagrams for more details. common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can start reset#=v id (note 1) perform erase or program operations reset#=v ih temporary sector unprotect completed ( note 2 ) notes: 1. all protected sectors unprotected. 2. previously protected sectors protected again.
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 10 en29lv160 rev. a, issue date: 2004 / 03 / 30 then be device-independent, jedec id- independent, and forward- and backward- compatible for the specified flash device families. flash vendirs can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 5-8. in word mode, the upper address bits (a7?msb) must be all zeros. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode and the system can read cfi data at the addresses given in tables 5?8. the system must write the reset command to return the device to the autoselect mode. table 5. cfi query identification string adresses (word mode) adresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists table 6. system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h vcc min (write/erase) d7-d4: volt, d3 ?d0: 100 millivolt 1ch 38h 0036h vcc max (write/erase) d7-d4: volt, d3 ?d0: 100 millivolt 1dh 3ah 0000h vpp min. voltage (00h = no vpp pin present) 1eh 3ch 0000h vpp max. voltage (00h = no vpp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2^n s 20h 40h 0000h typical timeout for min, size buffer write 2^n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2^n ms 22h 44h 0000h typical timeout for full chip erase 2^n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2^n times typical 24h 48h 0000h max. timeout for buffer write 2^n times typical 25h 4ah 0004h max. timeout per individual block erase 2^n times typical 26h 4ch 0000h max timeout for full chip erase 2^n times typical (00h = not supported) table 7. device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0015h device size = 2^n byte
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 11 en29lv160 rev. a, issue date: 2004 / 03 / 30 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2^n (00h = not supported) 2ch 58h 0004h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0000h 0000h 0040h 0000h erase block region 1 information (refer to the cfi specification of cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0020h 0000h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0080h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 001eh 0000h 0000h 0001h erase block region 4 information table 8. primary vendor-specific extended query adresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0030h minor version number, ascii 45h 8ah 0000h address sensitive unlock 0 = required, 1 = not required 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800a mode 4ah 94h 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 12 en29lv160 rev. a, issue date: 2004 / 03 / 30 hardware data protection the command sequence re quirement of unlock cycles for programming or er asing provides data protection against inadvertent writes as seen in the command definitions table. additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level sig nals during vcc power up and power do wn transitions, or from system noise. low v cc write inhibit when vcc is less than v lko , the device does not accept any write cycles. this protects data during vcc power up and power down. the command register and all internal program/eras e circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than v lko . the system must provide the proper signals to the control pins to prev ent unintentional writes when vcc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe , ce or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe = vil, ce = vih, or we = vih. to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. if ce , we , and oe are all logical zero (not recommended usag e), it will be co nsidered a read. power-up write inhibit during power-up, the device automatically resets to read mode and locks out write cycles. even with ce = v il , we = v il and oe = v ih , the device will not accept commands on the rising edge of we .
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 13 en29lv160 rev. a, issue date: 2004 / 03 / 30 command definitions the operations of the en29lv160 are selected by one or more commands written into the command register to perform read/reset memory, read id, read sector protection, program, sector erase, chip erase, erase suspend and erase resume. commands are made up of data sequences written at specific addresses via the command register. the sequences for the specified operation are defined in the command definitions table (table 5). incorrect addresses, incorrect data values or im proper sequences will reset the device to read mode. table 9. en29lv160 command definitions bus cycles 1 st write cycle 2 nd write cycle 3 rd write cycle 4 th write cycle 5 th write cycle 6 th write cycle command sequence cycles add data add data add data add data add data add data read 1 ra rd reset 1 xxx f0 word 555 2aa 555 000/ 100 7f/ 1c manufacturer id byte 4 aaa aa 555 55 aaa 90 000/ 200 7f/ 1c word 555 2aa 555 x01 22c4 device id top boot byte 4 aaa aa 555 55 aaa 90 x02 c4 word 555 2aa 555 x01 2249 device id bottom boot byte 4 aaa aa 555 55 aaa 90 x02 49 xx00 word 555 2aa 555 (sa) x02 xx01 00 autoselect sector protect verify byte 4 aaa aa 555 55 aaa 90 (sa) x04 01 word 555 2aa 555 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 unlock bypass byte 3 aaa aa 555 55 aaa 20 unlock bypass program 2 xxx a0 pa pd unlock bypass reset 2 xxx 90 xxx 00 word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 word 555 2aa 555 555 2aa sector erase byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend 1 xxx b0 erase resume 1 xxx 30 address and data values indicated in hex ra = read address: address of the memory location to be read. this is a read cycle. rd = read data: data read from location ra during read operation. this is a read cycle. pa = program address: address of the memory location to be programmed. x = don?t-care pd = program data: data to be programmed at location pa sa = sector address: address of the sector to be erased or verified. address bits a19-a12 uniquely select any sector. reading array data the device is automatically set to reading array data after power up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. following an erase suspend command, erase suspend m ode is entered. the system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors, the device outputs status data. after completi ng a programming operation in the erase suspend mode, the system may once again read array data with the same exception.
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 14 en29lv160 rev. a, issue date: 2004 / 03 / 30 the reset command must be issued to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see next section for details on reset. reset command writing the reset command to the device resets the device to reading array data. address bits are don?t- care for this command. the reset command may be written between the sequen ce cycles in an erase co mmand sequence before erasing begins. this resets the device to reading ar ray data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequen ce cycles in an autose lect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset comman d returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to acce ss the manufacturer and devices codes, and determine whether or not a sector is pr otected. the command definitions table shows the address and data requirements. this is an alternative to the method that requires v id on address bit a9 and is intended for prom programmers. two unlock cycles followed by the autoselect command initiate the autoselect command sequence. autoselect mode is then entered and the system may read at addresses shown in table 4 any number of times, without needing another command sequence. the system must write the reset comma nd to exit the autoselect mode and return to re ading array data. word / byte programming command the device may be programmed by byte or by word, depending on the state of the byte# pin. programming the en29lv160 is performed by using a four bus-cycle operation (two unlock write cycles followed by the program setup command and program data write cycle). when the program command is executed, no additional cpu controls or timings are necessary. an internal timer terminates the program operation automatically. address is latched on the falling edge of ce or we , whichever is last; data is latched on the rising edge of ce or we , whichever is first. programming status may be checked by sampling data on dq7 ( dat a polling) or on dq6 (toggle bit). ). when the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. note that data can not be programmed from a 0 to a 1. only an erase operation can change a data from 0 to 1. when programming time limit is exce eded, dq5 will produce a logica l ?1? and a reset command can return the device to read mode. unlock bypass to speed up programming operation, the unlock bypass command may be used. once this feature is activated, the shorter two cycle unlock bypass program command can be used instead of the normal four cycle program command to program the device. this mode is exited after issuing the unlock bypass reset command. the device powers up with this feature disabled.
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 15 en29lv160 rev. a, issue date: 2004 / 03 / 30 chip erase command chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up co mmand. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram pr ior to erase. the embedd ed erase algorithm automa tically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded chip erase algorithm are ignored. the system can determine the status of the erase operation by using dq7, dq6, or dq2. see ?write operation status? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. flowchart 4 illustrates the algorithm for the erase operation. see the erase/program operations tables in ?ac characteristics? for parameters, and to the chip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un-lock cycles, followed by a set-up command. two add itional unlock write cycles are then followed by the address of the sector to be erased, and the sect or erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the st atus of the erase operation by using dq7, dq6, or dq2. refer to ?write oper ation status? for in formation on these status bi ts. flowchart 4 illustrates the algorithm for the erase operation. refer to the erase/program operations tables in the ?ac characteristics? section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend / resume command the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected fo r erasure. this command is valid only during the sector erase operation. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. addresses are don?t-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. after the erase operation has been suspended, the system can read arra y data from or program data to any sector not selected for erasur e. (the device ?erase suspends? all sectors selected for erasure.) normal read and write timings an d command definitions apply. reading at any address within erase- suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasin g or is erase-suspended. see ?write operation status? for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 16 en29lv160 rev. a, issue date: 2004 / 03 / 30 dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the autoselect command is not supported during erase suspend mode. the system must write the erase resume command (a ddress bits are don?t-ca re) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. write operation status dq7 dat a polling the en29lv160 provides data polling on dq7 to indicate to the host system the status of the embedded operations. the data polling feature is active during the byte programming, sector erase, chip erase, erase suspend. (see table 6) when the byte programming is in progress, an attempt to read the device will produce the complement of the data last written to dq7. upon the completion of the byte programming, an attempt to read the device will produce the true data last written to dq7. for the byte programming, data polling is valid after the rising edge of the fourth we or ce pulse in the four-cycle sequence. when the embedded erase is in progress, an attemp t to read the device will produce a ?0? at the dq7 output. upon the completion of the embedded erase, the device will produce the ?1? at the dq7 output during the read. for chip erase, the data polling is valid after the rising edge of the sixth we or ce pulse in the six-cycle sequence. for sector erase, data polling is valid after the last rising edge of the sector erase we or ce pulse. data polling must be performed at any address wi thin a sector that is being programmed or erased and not a protected sector. otherwise, data polling may give an inaccurate result if the address used is in a protected sector. just prior to the completion of the embedded operations, dq7 may change asynchronously when the output enable ( oe ) is low. this means that the device is driving status information on dq7 at one instant of time and valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status of valid data. even if the device has completed the embedded operations and dq7 has a valid data, the data output on dq0-dq6 may be still invalid. the valid data on dq0-dq7 will be re ad on the subsequent read attempts. the flowchart for data polling (dq7) is shown on flowchart 5. the data polling (dq7) timing diagram is shown in figure 8. ry/by: ready/busy the ry/by is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by status is valid after the rising edge of the final we pulse in the command sequence. since ry/by is an open-drain output, several ry/by pins can be tied together in parallel with a pull-u p resistor to vcc. in the output is low, signifying busy, the device is actively erasing or programming. this includes programming in the erase suspend mode. if the output is high, signifying the ready, the device is ready to read array data (including during the erase suspend mode), or is in the standby mode.
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 17 en29lv160 rev. a, issue date: 2004 / 03 / 30 dq6 toggle bit i the en29lv160 provides a ?toggle bit? on dq6 to indicate to the host system the status of the embedded programming and erase operations. (see table 6) during an embedded program or erase operation, successive attempts to read data from the device at any address (by toggling oe or ce ) will result in dq6 toggling bet ween ?zero? and ?one?. once the embedded program or erase operation is comple te, dq6 will stop toggling and valid data will be read on the next successive attempts. during byte programming, the toggle bit is valid after the rising edge of the fourth we pulse in the four-cycle sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth-cycle sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. in byte programming, if the sector being writte n to is protected, dq6 will toggles for about 2 s, then stop toggling without the data in the sector having changed. in sector erase or chip erase, if all selected blocks are protected, dq6 will toggle for about 100 s. the chip will then return to the read mode without changing data in all protected blocks. toggling either ce or oe will cause dq6 to toggle. the flowchart for the toggle bit (dq6) is shown in flowchart 6. the toggle bit timing diagram is shown in figure 9 . dq5 exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. since it is possible that dq5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the dq6 is toggling after detecting a ?1? on dq5. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3 sector erase timer after writing a sector erase command sequence, the output on dq3 can be used to determine whether or not an erase operation has begun. (the sector erase ti mer does not apply to the chip erase command.) when sector erase starts, dq3 switches from ?0? to ?1 .? this device does no t support multiple sector erase command sequences so it is not very meaningful since it immediately shows as a ?1? after the first 30h command. future devices may support this feature. dq2 erase toggle bit ii the ?toggle bit? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising e dge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within th ose sectors that have been select ed for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 18 en29lv160 rev. a, issue date: 2004 / 03 / 30 status bits are required for sector and mode information. refer to table 5 to compare outputs for dq2 and dq6. flowchart 6 shows the toggle bit algorithm, and the sect ion ?dq2: toggle bit? explains the algorithm. see also the ?dq6: toggle bit i? subsec tion. refer to the toggl e bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to flowchart 6 for the following discussion. when ever the system initially be gins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and stor e the value of the toggle bit afte r the first read. after the second read, the system would compare the new va lue of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or er ase operation. the system can read array data on dq7?dq0 on the follo wing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operat ion. if it is still toggling, the dev ice did not complete the operation successfully, and the system must write the rese t command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monito r the toggle bit and dq5 through successive read cycles, determining the status as described in the pr evious paragraph. alternatively, it may choose to perform other system tasks. in this ca se, the system must start at the be ginning of the algorithm when it returns to determine the status of the operation (top of flowchart 6). write operation status operation dq7 dq6 dq5 dq3 dq2 ry/by # embedded program algorithm dq7# toggle 0 n/a no toggle 0 standar d mode embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase suspend mode erase-suspend program dq7# toggle 0 n/a n/a 0
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 19 en29lv160 rev. a, issue date: 2004 / 03 / 30 table 10. status register bits dq name logic level definition ?1? erase complete or erase sector in erase suspend ?0? erase on-going dq7 program complete or data of non-erase sector during erase suspend 7 data polling dq7# program on-going ?-1-0-1-0-1-0-1-? erase or program on-going dq6 read during erase suspend 6 toggle bit ?-1-1-1-1-1-1-1-? erase complete ?1? program or erase error 5 error bit ?0? program or erase on-going ?1? erase operation start 3 erase time bit ?0? erase timeout period on-going ?-1-0-1-0-1-0-1-? chip erase, erase or erase suspend on currently addressed sector. (when dq5=1, erase error due to currently addressed sector. program during erase suspend on- going at current address 2 toggle bit dq2 erase suspend read on non erase suspend sector notes: dq7 data polling: indicates the p/e status check during program or erase, and on completion before checking bits dq5 for program or erase success. dq6 toggle bit: remains at constant level when p/e operations are complete or erase suspend is acknowledged. successive reads output complementary data on dq6 while programming or erase operation are on-going. dq5 error bit: set to ?1? if failure in programming or erase dq3 sector erase command timeout bit: operation has started. only possible command is erase suspend (es). dq2 toggle bit: indicates the erase status and allows identification of the erased sector.
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 20 en29lv160 rev. a, issue date: 2004 / 03 / 30 embedded algorithms flowchart 1. embedded program start write program command sequence (shown below) data poll device last address? programming done increment address no yes verify data? flowchart 2. embedded program command sequence see the command definitions section for more information. 2aah / 55h 555h / aah 555h / a0h program address / program data
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 21 en29lv160 rev. a, issue date: 2004 / 03 / 30 flowchart 3. embedded erase start write erase command sequence data poll from system or toggle bit successfully completed erase done data =ffh? yes no
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 22 en29lv160 rev. a, issue date: 2004 / 03 / 30 flowchart 4. embedded erase command sequence see the command definitions section for more information. chip erase sector erase 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 555h/aah 2aah/55h 555h/80h 555h/aah 2aah/55h sector address/30h
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 23 en29lv160 rev. a, issue date: 2004 / 03 / 30 flowchart 5. dat a polling algorithm notes: (1) this second read is necessary in case the first read was done at the exact instant when the status data was in transition. flowchart 6. toggle bit algorithm notes: (1) this second set of reads is necessary in case the first set of reads was done at the exact instant when the status data was in transition. no yes dq6 = toggle? dq5 = 1? dq6 = toggle? no no yes yes read data twice start read data twice (2) fail pass no no dq7 = data? dq5 = 1? dq7 = data? yes yes no yes read data start read data (1) fail pass
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 24 en29lv160 rev. a, issue date: 2004 / 03 / 30 flowchart 7a. in-system sector protect flowchart start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? no temporary sector unprotect mode yes set up sector address sector protect: write 60h to sector addr with a 6 = 0, a1 = 1, a0 = 0 wait 150 s verify sector protect: write 40h to sector address with a 6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 data = 01h? no plscnt = 25? increment plscnt no device failed yes protect another sector? yes reset plscnt = 1 no remove v id from reset# write reset command sector protect complete sector protect algorithm yes wait 0.4 s
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 25 en29lv160 rev. a, issue date: 2004 / 03 / 30 flowchart 7b. in-system sector unprotect flowchart start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? temporary sector unprotect mode no yes all sectors protected? yes no protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address (see diagram 7a.) set up first sector address sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 =0 read from sector address with a6 = 1, a1 = 1, a0 = 0 data = 00h? no plsccnt = 1000? no increment plscnt yes device failed last sector verified? no set up next sector address remove v id from reset# write reset command sector unprotect com p lete sector unprotect algorithm wait 0.4 s yes yes
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 26 en29lv160 rev. a, issue date: 2004 / 03 / 30 table 11. dc characteristics (t a = 0c to 70c or - 40c to 85c; v cc = 2.7-3.6v) notes 1. byte# pin can also be gnd 0.3v. byte# and reset# pin input buffers are always enabled so that they draw power if not at full cmos supply voltages. symbol parameter test conditions min typ max unit i li input leakage current 0v v in vcc 5 a i lo output leakage current 0v v out vcc 5 a supply current (read) cmos byte 9 16 ma i cc1 (read) cmos word ce# = v il ; oe# = v ih ; f = 5mhz 9 16 ma supply current (standby - ttl) ce# = v ih , byte# = reset# = vcc 0.3v (note 1) 0.4 1.0 ma i cc2 (standby - cmos) ce# = byte# = reset# = vcc 0.3v (note 1) 1 5.0 a i cc3 supply current (program or erase) byte program, sector or chip erase in progress 20 30 ma v il input low voltage -0.5 0.8 v v ih input high voltage 0.7 x vcc vcc 0.3 v v ol output low voltage i ol = 4.0 ma 0.45 v output high voltage ttl i oh = -2.0 ma 0.85 x vcc v v oh output high voltage cmos i oh = -100 a, vcc - 0.4v v v id a9 voltage (electronic signature) 10.5 11.5 v i id a9 current (electronic signature) a9 = v id 100 a v lko supply voltage (erase and program lock-out) 2.3 2.5 v
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 27 en29lv160 rev. a, issue date: 2004 / 03 / 30 test conditions test specifications ac characteristics hardware reset (reset#) speed options unit parameter std description test setup -70 -90 t ready reset# pin low to read or write embedded algorithms max 20 s t ready reset# pin low to read or write non embedded algorithms max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read min 50 ns test conditions -70 -90 unit output load 1 ttl gate output load capacitance, c l 30 100 pf input rise and fall times 5 5 ns input pulse levels 0.0-3.0 0.0-3.0 v input timing measurement reference levels 1.5 1.5 v output timing measurement reference levels 1.5 1.5 v device under test c l 6.2 k ? 2.7 k ? 3.3 v note: diodes are in3064 or equivalent
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 28 en29lv160 rev. a, issue date: 2004 / 03 / 30 reset# timings t rh t rp t ready 0 v ry/by# ce# oe# reset# reset timings not during automatic algorithms t ready t rh t rp ry/by# ce# oe# reset# reset timings during automatic algorithms
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 29 en29lv160 rev. a, issue date: 2004 / 03 / 30 ac characteristics word / byte configuration (byte#) speed unit std parameter description -70 -90 t bcs byte# to ce# switching setup time min 0 0 ns t cbh ce# to byte# switching hold time min 0 0 ns t rbh ry/by# to byte# switching hold time min 0 0 ns byte timings for read operations byte timings for write operations note: switching byte# pin not allowed during embedded operations t bcs ce oe byte ce we t cbh t bcs byte t rbh ry/by
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 30 en29lv160 rev. a, issue date: 2004 / 03 / 30 table 12. ac characteristics read-only operations characteristics parameter symbols speed options jedec standard description test setup -70 -90 unit t avav t rc read cycle time min 70 90 ns t avqv t acc address to output delay ce = v il oe = v il max 70 90 ns t elqv t ce chip enable to output delay oe = v il max 70 90 ns t glqv t oe output enable to output delay max 30 35 ns t ehqz t df chip enable to output high z max 20 20 ns t ghqz t df output enable to output high z max 20 20 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min 0 0 ns notes: for - 70 vcc = 3.0v 5% output load : 1 ttl gate and 30pf input rise and fall times: 5ns input rise levels: 0.0 v to 3.0 v timing measurement reference level, input and output: 1.5 v for all others: vcc = 2.7v ? 3.6v output load: 1 ttl gate and 100 pf input rise and fall times: 5 ns input pulse levels: 0.45 v to .8 x vcc timing measurement reference level, input and output: 0.8 v and .7 x vcc figure 5. ac waveforms for read operations addresses ce# oe# we# outputs reset# ry/by# 0v output valid t rc t acc t oe t ce t oeh t oh t df high z a ddresses stable
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 31 en29lv160 rev. a, issue date: 2004 / 03 / 30 table 13. ac characteristics write (erase/program) operations parameter symbols speed options jedec standard description -70 -90 unit t avav t wc write cycle time min 70 90 ns t avwl t as address setup time min 0 0 ns t wlax t ah address hold time min 45 45 ns t dvwh t ds data setup time min 30 45 ns t whdx t dh data hold time min 0 0 ns t oes output enable setup time min 0 0 ns read min 0 0 ns t oeh output enable hold time toggle and data polling min 10 10 ns t ghwl t ghwl read recovery time before write ( oe high to we low) min 0 0 ns t elwl t cs ce setuptime min 0 0 ns t wheh t ch ce hold time min 0 0 ns t wlwh t wp write pulse width min 45 45 ns t whdl t wph write pulse width high min 20 20 ns typ 8 8 s t whwh1 t whwh1 programming operation (word and byte mode) max 300 300 s typ 0.5 0.5 s t whwh2 t whwh2 sector erase operation max 10 10 s typ 17.5 17.5 s t whwh3 t whwh3 chip erase operation max s t vcs vcc setup time min 50 50 s t vidr rise time to v id min 500 500 ns
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 32 en29lv160 rev. a, issue date: 2004 / 03 / 30 table 14. ac characteristics write (erase/program) operations alternate ce controlled writes parameter symbols speed options jedec standard description -70 -90 unit t avav t wc write cycle time min 70 90 ns t avel t as address setup time min 0 0 ns t elax t ah address hold time min 45 45 ns t dveh t ds data setup time min 30 45 ns t ehdx t dh data hold time min 0 0 ns t oes output enable setup time min 0 0 ns t oeh output enable read 0 0 0 ns hold time toggle and data polling 10 10 10 ns t ghel t ghel read recovery time before write ( oe high to ce low) min 0 0 ns t wlel t ws we setuptime min 0 0 ns t ehwh t wh we hold time min 0 0 ns t eleh t cp write pulse width min 35 45 ns t ehel t cph write pulse width high min 20 20 ns typ 8 8 s t whwh1 t whwh1 programming operation (byte and word mode) max 300 300 s typ 0.5 0.5 s t whwh2 t whwh2 sector erase operation max 10 10 s typ 17.5 17.5 s t whwh3 t whwh3 chip erase operation max s t vcs vcc setup time min 50 50 s t vidr rise time to v id min 500 500 ns
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 33 en29lv160 rev. a, issue date: 2004 / 03 / 30 table 15. erase and programming performance limits parameter typ max unit comments sector erase time 0.5 10 sec chip erase time 17.5 sec excludes 00h programming prior to erasure byte programming time 8 300 s word programming time 8 300 s byte 16.8 50.4 chip programming time word 8.4 25.2 sec excludes system level overhead erase/program endurance 100k cycles minimum 100k cycles table 16. latch up characteristics parameter description min max input voltage with respect to v ss on all pins except i/o pins (including a9, reset and oe ) -1.0 v 12.0 v input voltage with respect to v ss on all i/o pins -1.0 v vcc + 1.0 v vcc current -100 ma 100 ma note : these are latch up characteristics and the device should never be put under these conditions. refer to absolute maximum ratings for the actual operating limits. table 17. 48-pin tsop pin capacitance @ 25c, 1.0mhz parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf table 18. data retention parameter description test conditions min unit 150c 10 years minimum pattern data retention time 125c 20 years
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 34 en29lv160 rev. a, issue date: 2004 / 03 / 30 ac characteristics figure 6. ac waveforms for chip/sector erase operations timings notes: 1. sa=sector address (for sector erase) , va=valid address for reading status, d out =true data at read address. 2. v cc shown only to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. t dh t ds t busy t wph t ch t wp t cs t vcs t rb t wc t as t ah t ghwl t whwh2 or t whwh3 0x2aa sa va va 0x55 0x30 status d out a ddresses ce# oe# we# data ry/by# v cc 0x555 for chip erase erase command sequence (last 2 cycles) read status data (last two cycles)
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 35 en29lv160 rev. a, issue date: 2004 / 03 / 30 figure 7. program operation timings notes: 1. pa=program address, pd=program data, d out is the true data at the program address. 2. v cc shown in order to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. t vcs t dh t rb t whwh1 t busy t ds t cs t wph t ch t wp t ghwl t wc t as t ah 0x555 pa pa pa pd status d out oxa0 a ddresses ce# oe# we# data ry/by# v cc program command sequence (last 2 cycles) program command sequence (last 2 cycles)
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 36 en29lv160 rev. a, issue date: 2004 / 03 / 30 figure 8. ac waveforms for /data polling during embedded algorithm operations notes: 1. va=valid address for reading data# polling status data 2. this diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cy cle. figure 9. ac waveforms for toggle bit during embedded algorithm operations t oeh t df t oh t busy t oe complement status data comple- ment true true status data valid data valid data t ce t acc t ch t rc va va va a ddresses ce# oe# we# dq[7] dq[6:0] ry/by# t rc t acc t ce t oe t oeh t ch t df t oh t busy va va va va valid status valid status valid status valid data (first read) (second d) (stops toggling) a ddresses ce# oe# we# dq6, dq2 ry/by#
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 37 en29lv160 rev. a, issue date: 2004 / 03 / 30 figure 10. alternate ce# controlled write operation timings notes: pa = address of the memory location to be programmed. pd = data to be programmed at byte address. va = valid address for reading program or erase status d out = array data read at va shown above are the last two cycles of the program or erase command sequence and the last status read cycle reset# shown to illustrate t rh measurement references. it cannot occur as shown during a valid command sequence. figure 11. dq2 vs. dq6 we# dq6 dq2 enter embedded erase erase suspend enter erase suspend program erase resume erase enter suspend read enter suspend program erase erase complete erase suspend read t wc t rh t as t ah t wh t ghel t cph t cp t ws t dh t ds t busy t cwhwh1 / t cwhwh2 / t cwhwh3 status d out 0xa0 for program pd for program 0x30 for sector erase 0x10 for chip erase va a ddresses we# oe# ce# data ry/by# reset# pa for program sa for sector erase 0x555 for chip erase 0x555 for program 0x2aa for erase
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 38 en29lv160 rev. a, issue date: 2004 / 03 / 30 temporary sector unprotect speed option unit parameter std description -70 -90 t vidr v id rise and fall time min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s figure 12. temporary sector unprotect timing diagram 0 or 3 v reset# t vidr t vidr t rsp v id 0 or 3 v ce# we# ry/by#
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 39 en29lv160 rev. a, issue date: 2004 / 03 / 30 figure 13. sector protect/unprotect timing diagram notes: use standard microprocessor timings for this device for read and write cycles. for sector protect, use a6=0, a1=1, a0=0. for sector unprotect, use a6=1, a1=1, a0=0. v id sa, a6,a1,a0 reset# 0 v t vidr t vidr >1
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 40 en29lv160 rev. a, issue date: 2004 / 03 / 30 figure 14. tsop 12mm x 20mm
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 41 en29lv160 rev. a, issue date: 2004 / 03 / 30
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 42 en29lv160 rev. a, issue date: 2004 / 03 / 30 figure 15. 48tfbga package outline
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 43 en29lv160 rev. a, issue date: 2004 / 03 / 30 absolute maximum ratings parameter value unit storage temperature -65 to +125 c plastic packages -65 to +125 c ambient temperature with power applied -55 to +125 c output short circuit current 1 200 ma a9, oe#, reset# 2 -0.5 to +11.5 v all other pins 3 -0.5 to vcc+0.5 v voltage with respect to ground vcc -0.5 to +4.0 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc input voltage on a9, oe#, reset# pins is ?0. 5v. during voltage transitions, a9, oe#, reset# pins may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0v for periods of up to 20ns. see figure below. maximum dc input voltage on a9, oe#, and reset# is 11.5v which may overshoot to 12.5v for periods up to 20ns. 3. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 1.5 v for periods up to 20ns. see figure below. 4. stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. recommended operating ranges 1 parameter value unit ambient operating temperature commercial devices industrial devices 0 to 70 -40 to 85 c regulated voltage range: 3.0-3.6v operating supply voltage vcc full voltage range: 2.7 to 3.6v v 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. vcc +1.5v maximum negative overshoot maximum positive overshoot waveform waveform
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 44 en29lv160 rev. a, issue date: 2004 / 03 / 30 ordering information en29lv160 t - 70 t c p packaging content (blank) = conventional p = pb free temperature range (blank) = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package t = 48-pin tsop b = 48-ball fine pitch ball grid array (fbga) 0.80mm pitch, 6mm x 8mm pa ckage speed 70 = 70ns 90 = 90ns boot code sector architecture t = top boot sector b = bottom boot sector base part number en = eon silicon solution inc. 29lv = flash, 3v read program erase 160 = 16 megabit (2m x 8 / 1m x 16)
this data sheet may be revised by subsequent versions ?2003 eon silicon solution, inc., www.essi.com.tw or modifications due to changes in technical specifications. 45 en29lv160 rev. a, issue date: 2004 / 03 / 30 revisions list revision no description date a preliminary draft 3/30/2004

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